Senior Analog Layout Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

AMD is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting-edge foundry technology. Examples of layout designed by our team include Phase Locked Loop (PLL), Delay Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signalling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.

THE PERSON

An experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious.

KEY RESPONSIBILITIES

Layout of basic digital and analog building blocks using analog transistor level components.

Layout of analog macros, power pads, and input/output pads using above blocks

Working closely with Analog designers in floorplanning; power grid and signal flow planning

Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD

Creation of blackbox models for other groups in the design flow

PREFERRED EXPERIENCE

Must have detailed knowledge of CMOS circuit theory.

Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout

Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools

Must have at least 5 years of relevant or comparable experience doing analog layout design

Knowledge of chip level integration and ESD concepts a plus

Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability

Good understanding of signal and clock shielding and isolation techniques

Ability to work well as part of a team

ACADEMIC CREDENTIALS

Bachelor’s degree in Engineering (or related field) OR Associates Degree in Engineering.

LOCATION:

Penang, Malaysia

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.