ASIC Design Verification Engineer

Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification
Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance
Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral modules for both block levels and system levels
Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out
Work with design engineers to debug and identify root causes of simulation failure
Support test engineers for post-silicon validation
Mentor and coach junior engineers. Drive verification efficiency

Qualifications

MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree

In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology

Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and test cases development for function/performance verification

Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding

Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core

Experience in verifying designs at both RTL level and post-P&R gate level

Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus

• Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators
• Experience in verifying mix-signal design and interface of digital and analog
• Experience of design verification for high-speed IO such as PCIE and DDR

Additional Information

All your information will be kept confidential according to EEO guidelines.